Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Constrainst for data launched by negative edge

Hi, What is the correct way to constrains source synchronous inputs in this case:External device provides clock with data. External device launches data on falling edge. FPGA latches dat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

Thank you Bhaumik.

--- Quote Start ---

one question : Which clock have you been using to capture data? Are you using clock directly coming into FPGA?

--- Quote End ---

I am using CLK_IN which directly comes to FPGA, PLL is not used.