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Honored Contributor
Honored ContributorConstrainst for data launched by negative edge
Hi, What is the correct way to constrains source synchronous inputs in this case:External device provides clock with data. External device launches data on falling edge. FPGA latches dat...
Altera_ForumHonored Contributor
Honored ContributorHi,
Thank you Bhaumik. --- Quote Start --- one question : Which clock have you been using to capture data? Are you using clock directly coming into FPGA? --- Quote End --- I am using CLK_IN which directly comes to FPGA, PLL is not used.
