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Altera_Forum
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9 years ago

Constraining Derived External Clocks

I have an external reference clock coming into the fabric through the PLL (lets call it clk1 at the output of the PLL) I then divide this clock and send it out to the pins to an external (board) c...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Hi Kaz, thank you so much for kind reply. will this set_clock_latency take care of the routing delay from fabric to pad and back for the derived clock?