Constraining ADC output to Stratix IV GX board

Hi everyone,

I am using a 12bits differential ADC with a clock rate of 245.76MHz interfaced with the Altera Stratix IV GX board by the HSMC connector.

I am trying to add timing constaints to my design but I don't know how much input delay I should mention.

I have only an information about the data output from the ADC which has a data to clock skew of -0.3ns minimum and 0.5ns maximum.

Please help me in that issue ASAP I am really in rush.

Thank you.