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Altera_Forum's avatar
Altera_Forum
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12 years ago

Constrain SDR and DDR interface on the same interface

Hello, I have an IC that is outputting a databus with a center aligned clock. Depending on its mode, it is outputting in single data rate (up to 200MHz) or in dual data rate (up to 100MHz). ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The falling edge registers are indeed ignored in SDR mode.

I was wrong in my post, I do use the -waveform but on the clock coming into the FPGA. Thus using option 2.

Thanks for making things clear to me!