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Altera_Forum
Honored Contributor
Honored ContributorConstants in Verilog
Hi, I have a IP coded in verilog. The simulator used in Modelsim and Synthesizer is Quartus II. This IP is going to Stratix FPGA with other IP's. I am confused about the usage of 'define and ...
Altera_ForumHonored Contributor
Honored ContributorThat was a nice read. Thanks for the link.
I had to laugh every time he slammed authors of other books for what he deemed as "mis-information". He was quite opinionated, but backed it up nicely with his explainations and examples.
