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How many buffers should be used here? on the handbook there is only two Cyclone III devices and there is a buffer between the devices. But should we put additional buffers if there are more than two devices?
i mean, one buffer after each device?
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Generally for clocks you want point-to-point routes on a PCB. Most buffers can drive a couple of source-terminated loads, so one buffer can be used to generate a couple of TCK and TMS fanouts. Take a look at the CARMA board design that I posted links to, look in the schematic:
http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (
http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)
Page 7 has the JTAG high-level diagram. p44 has the Altera JTAG buffers. Note how the buffers have series terminations on their output - this is so that one buffer can drive multiple TCK and TMS traces. p77 shows some more buffering with dual-source terminations. p78 shows the inter-FPGA JTAG TDI/TDO chains. Since the I/O levels are 2.5V, the FPGAs can be connected directly. If the FPGA TDO driver was being powered from an I/O bank voltage of 1.8V, then a 1.8V-to-2.5V (or 3.3V) level translation buffer would be required when buffering between FPGAs. I have a buffer on the CEO# signal so that a red LED is turned off once the FPGAs are configured. This is nice for debugging.
Cheers,
Dave
Honored Contributor
