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Altera_Forum
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14 years ago

Configuring Cyclone3 EP3C25F256

Hi,

I am designing a board with EP3C25F256 and I have encountered a few unclear things in the cyclone 3 handbook. I would appreciate an explanation (sorry for the long post):

1. MSEL pins voltage - Page 171 says: "Hardwire the MSEL pins to VCCA or GND without any pull-up or pull-down resistors to avoid any problems detecting an incorrect configuration scheme", while VCCA is 2.5V. Below on the same page table 9-7 says that for AS standard configuration the voltage standard is 3.3V. Which one is correct?

2. I'm going to use JTAG with EPCS4, using the Serial Flash Loader option. I configured the MSEL pins to AS [2 1 0] = "010". Is there anything else (form HW point of view) that I should do in order to use that option?

3. JTAG - I've connected the JTAG pins to 3.3V (VCCIO), because of the following (page 208):" The TDO output pin is powered by VCCIO in I/O bank 1. All the JTAG input pins are powered by the VCCIO pin". However, figure 9-24 connects the JTAG pins to VCCA and not VCCIO. Also, it says in the Cyclone® III Device Family Pin Connection Guidelines: "When interfacing with 2.5V/3.0V/3.3V configuration voltage standards, connect this pin through a 1-kOhm resistor to VCCA". Am I wrong here?

Thanks in advance

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Altera's suggestions for your configuration are summed up in Figure 9-30 (at page 9-60 of most recent device handbook release V3.3).

    There have been previous forum discussions, why the suggestions are so, and if you have to follow it strictly. Personally, I don't, but if you don't see any contradicting reasons, you simply can, because they are supposed to work.

    Without repeating this discussions, I want to mention two aspects:

    VCCA rather than VCCIO is used to set the MSEL configuration, because VCCA is monitored by the POR circuitry. The objective is to read a correct and stable configuration when POR is released.

    With Cyclone III, Altera is worried about the risk of damaging I/O pins by signal overshoots. This is e.g. reflected when supplying the JTAG interface by 2.5 V. There are howver alternatives like using an effective clamping circuit.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi FvM,

    Thanks for the quick answer. Any comments on question 2?

    Thanks