Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorConditional assignments with generics
Is it possible in VHDL to assign a signal conditionally based on the value of a generics without creating additional unwanted logic? I think the following code created logic to evaluate the...
Altera_ForumHonored Contributor
Honored ContributorGenerally, Quartus isn't generating any unwanted logic. It's removing unneeded signals and registers unless explicitely told to keep it by synthesis attributes. The only disadvantage of using generics in conditional expresions is that you get some warnings regarding constant expressions. But it's the only plausible method to achieve conditional compilation inside a process, so the warnings should be accepted. You can expect a lot of similar meaningless warnings with parameterizable designs.
Cause place and route is performed after minimizing logic expressions, I can't imagine why the synthesis should end up with different timing.
