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Altera_Forum
Honored Contributor
Honored ContributorConditional assignments with generics
Is it possible in VHDL to assign a signal conditionally based on the value of a generics without creating additional unwanted logic? I think the following code created logic to evaluate the...
Altera_ForumHonored Contributor
Honored ContributorIf one version fails timing, did you analyze the difference between the critical paths in the passing and failing versions. It could be that you're on the cusp of meeting timing and small netlist changes or random placement variations are enough to push you over or under your timing constraint(s).
