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Altera_Forum
Honored Contributor
Honored ContributorConditional assignments with generics
Is it possible in VHDL to assign a signal conditionally based on the value of a generics without creating additional unwanted logic? I think the following code created logic to evaluate the...
Altera_ForumHonored Contributor
Honored ContributorThanks for your reply. I tried the generate and the original way I had it and they both produce the same result. When the conditionals are in there, my design doesn't pass the timing requirement on those signals, but if I take the conditionals out it works just fine. Maybe it is a Quartus bug.
