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Honored Contributor
Honored ContributorConcurrent writes in multi-ported memories
Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Is this idea sensible? --- Quote End --- No. :) Provide a use-case where all four devices will write, and describe who should win, i.e., which write port should write. If the priority is static, then address comparators and an if statement is probably sufficient. If the priority is dynamic, then you would need a 4-bit register to determine "who gets to write next", eg., a shift-register with 1 bit set, that gets shifted once the writer corresponding to that bit gets to write, would be a round-robin scheduler. Although you can conceive of how to do this, its still not clear *why* you want or need to :) Cheers, Dave
