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Altera_Forum
Honored Contributor
Honored ContributorConcurrent writes in multi-ported memories
Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_ForumHonored Contributor
Honored ContributorBut I am confused over one thing. Won't the software code using synchronisation mechanisms make sure that writes are not issued to the same physical address in the same clock cycle? If it is resolved at the software level itself , why should we bother trying to add hardware features to resolve it?
