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In a multicore environment with shared memory when multiple threads are issued thread , if a thread is accessing critical section other threads are made to wait. Synchronisation mechanism like atomic instructions , locks etc are implemented. I was thinking if some analogy of that sort would work for a multi-port memory where there are multiple ports instead of multiple threads accessing the same memory. Am I thinking in the right direction? I want to do a hardware implementation (not software) to resolve the issue.
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The hardware generally provides "features" for the multiple processors to coordinate their shared access to a resource.
This type of issue comes up with PCI/PCIe device drivers too, eg., motherboard/host processor and peripheral board processor communications. Multiprocessor (eg., multiple NIOS II instances). Read the stuff on p7 of this document:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/cobra_driver.pdf The hardware interlock discussed there is used to implement a Linux device driver on the PCI host side, and a uC/OS-II driver on the peripheral board side. In both cases, the software has to use operating system primitives like semaphores and mutexes, eg., for the interrupt handler to restart a task that deals with communications.
You cannot avoid doing this type of thing when addressing a common resource.
Another typical scenario is communications using a scatter-gather DMA controller. The hardware implements the movement of data based on scatter-gather lists configured by software. When a list entry is moved between the software (eg., filling or removing data) to the hardware (eg., here's your empty list entry to re-use) then hardware interlocks are used, eg., the controller is disabled.
Cheers,
Dave
Honored Contributor
