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Altera_Forum
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12 years ago

Concurrent writes in multi-ported memories

Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi,

Yeah I guess we could solve it using 1) Priority 2) Let the ports write if they are writing the same data 3) Arbitrarily select one of the ports and let it write. I have read that Parallel Random Access Machines (PRAM) use these technique to solve the conflicts. But I don't know if there have been any hardware implementation of PRAMs!

In a multicore environment with shared memory when multiple threads are issued thread , if a thread is accessing critical section other threads are made to wait. Synchronisation mechanism like atomic instructions , locks etc are implemented. I was thinking if some analogy of that sort would work for a multi-port memory where there are multiple ports instead of multiple threads accessing the same memory. Am I thinking in the right direction? I want to do a hardware implementation (not software) to resolve the issue.

Thanks...