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Altera_Forum
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12 years ago

Concurrent writes in multi-ported memories

Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
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Altera_Forum
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12 years ago

Hi Dave,

I think what you are saying is about the read-during-write behavior right? But I was looking for conflicting writes ( what happens when more than 1 port, say in a 4W/8R memory try write to the same location in the same clock cycle).

There are algorithms for concurrent writes in a "shared memory" . But I couldn't find anything for multi-ported memories..