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Honored ContributorComplex dual tone generation
Hello, I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board,...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- make one counter start from 0 and increment by 2 (0,2,4,...) set other counter to start at 1 and increment by 2(1,3,5...) then the ddr output should be 0,1,2,3,4... assuming you feed the pair in that sense --- Quote End --- Hi Kaz, I have managed to simulate that, and I have found out that this is possibly just the way Model-Sim represents the data. I have made the second counter start from 5000 and the first from 0. When I run the simulation now I see clearly that the signals are switching with double data rate, so if the data I am interleaving are exactly the same, it´s basically always like having a single data rate, and Model-Sim doesn´t represent the signal´s switching, and this makes sense.... Thanks for your help!
