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MKlee2's avatar
MKlee2
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6 years ago
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Communication between two FPGAs (using altlvds ip?)

Hello, I need to implement a communication between two FPGAs, one Cyclone V and one Cyclone 10 LP. Both devices will be connected using a fiber cable, so I have one tx and one rx lane. Because of ...
  • Rahul_S_Intel1's avatar
    6 years ago
    Hi, May I know the below error is for the Error (11239): Location FRACTIONALPLL_X0_Y1_N0 is already occupied by pll_tx:pll_tx0|pll_tx_0002:pll_tx_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL. For which Cyclone part