communication about niosii uart

Hi,

The basic UART has a single character buffer, so the usual approach is to have the UART generate a RRDY interrupt when a new character is received, which you must read before the next character is received. So, the first character generates a RRDY interrupt, your ISR reads that character and may store it in a FIFO buffer in RAM, then returns from the ISR. The next character then generates another interrupt and so on. You can then process characters from the FIFO outside your ISR.

When the NIOS forum comes back online, you could search that for lots of information regarding this type of UART handling. Also, you may read there about a FIFO'd UART which I haven't used myself, but may well offer the type of behaviour you are after (I guess it handles the transfer of received characters into a FIFO in hardware).

Hope this helps

Sharkybaba