clock synchronization problem

Hi Everyone, Please I need help

I am designing speech recognition system on DE2 board.

I generated some Megafunction modules in Quartus II such as:

[32_bits LPM shiftreg] -- to convert from serial to parallel and vice versa,

[32_bits ALTFP] -- to convert from integer to float and vice versa,

I instantiate those four modules together as

-------------------- ------------- ------------- -------------------

- serial2parallel - -----> - int2float - -------> - float2int - --------> - parallel2serial-

-------------------- ------------- ------------- -------------------

My question is which clock should I use to drive speech data through those modules, I used 50MHZ but I got noisy signal in the output(speakers).