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Altera_Forum's avatar
Altera_Forum
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17 years ago

Clock skews, enables and timing

Can someone help me? I am new to this and have been learning from scratch to program FPGAS and windows at the same time whilst building hardware. I have written some code for a data capture s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hello,

With the second thought I find the blocking assignments are no harm with synthesis, but it may cause simulation issue. So I recommend you to use "<=" instead of "=" in the always.