Clock skews, enables and timing

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Can someone help me?

Someone mentioned on here that I need to use chip enable clocks to sort out the gated clock issue but I do not know how to do this?

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instead of passing a clock through a gate i.e. AND'd with some other signal you want to gate the clock with, feed the clock as normal into the clk inputs of the register(s) which follow i.e. are currently fed by your gated clock and then feed the gate signal into the clock enable (clken) input of the very same registers.