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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock skew problem

Hello, I am actually facing problems related to clock skew. Timing analisys reports a clock skew problem between the output of a latch and an input of a register( 40 bit wide bus ). I h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Sorry for the late reply... I have been busy with some other stupid stuff.

Anyway, I am back to the problem , which is solved now, thanks to you guys.

I followed the recommandation from Rysc, and indeed it working perfeclty, as I have no uge timing constraints ( just a speed loss of 2.5%,after turning on

the hold time optimization ).

Thanks Brad for the link to the ripple and gated clock, I found it very interesting.

Cheers