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Altera_Forum
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18 years ago

Clock skew problem

Hello, I am actually facing problems related to clock skew. Timing analisys reports a clock skew problem between the output of a latch and an input of a register( 40 bit wide bus ). I h...
Altera_Forum's avatar
Altera_Forum
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18 years ago

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... it's recommended to not gate clocks from the beginning. If the gated clock could be changed to a clock enable or something like that, then the structure is better from a good design practice standpoint.

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For more about this, see http://www.alteraforum.com/forum/showthread.php?t=2388.