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Honored Contributor
Honored ContributorClock skew problem
Hello, I am actually facing problems related to clock skew. Timing analisys reports a clock skew problem between the output of a latch and an input of a register( 40 bit wide bus ). I h...
Altera_ForumHonored Contributor
Honored ContributorCan you give more details? What FPGA are you using (model and speed grade). Which timing analysis tool are you using (Classic or Timequest)? How fast is the clock running? Can you give more details about the registers? What is the fanout of the source signal? Are any of the registers located in the I/O ring?
Jake
