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Altera_Forum
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17 years ago

Clock skew problem

Hello, I am actually facing problems related to clock skew. Timing analisys reports a clock skew problem between the output of a latch and an input of a register( 40 bit wide bus ). I h...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Hi Titouan,

you are right: If you insert just a signal in VHDL or Verilog then this local signal is removed. You can add LCELL modules to add a combinational delay and you even can increase the numner of LCELL inserted with the assignment editor. But this is not the way I'd propose. My advice: Try to make your design a synchronous design. And don't use a latch.

Regards,

Harald