Clock Skew doubt

A further practical issue:

When designing submodules, a common practice is to register the submodule outputs but not its inputs since inputs will acquire registers of front module at integration. When checking timing on the submodule as such then TimeQuest defaults to assuming that input/output ports are IOs but they are not and it cannot report on first set of registers because it does not have info on input signals. Similarly it cannot report on recovery/removal of reset which could be widespread in the submodule unless reset is passed first to a register but this is not the practice at submodule level.

Thus the timing report at submodule level is incomplete. One way to overcome that is add registers to all inputs and to reset temporarily for TimeQuest analysis only then remove them at integration as they will acquire registers at integration. The IO optimisation need also be set to off.

Alternatively some prefer set_false path to all IOs but I am not sure how accurate this is.