Clock Skew doubt

Here is my table summary of io timing settings:

Inputs methods                            outputs methods                         
 
(1) tCO of ext device output         (1) tSU/tH of ext device input       (system centric)                 
(2) tSU/tH of fpga input               (2) tCO of fpga output?                  (fpga centric)
(3) skew at fpga input                  (3) skew at fpga output                 (skew at fpga)
---------------------------------------------------------------------------------------------------------
 
Commands and equations:
 
(1) input
Set_input_delay –max  < max tCO of input device + max data delay – min clk delay >
Set_input_delay –min   < min tCO of input device  + min data delay – max clk delay >
 
(2) input
Set_input_delay –max  < UI – tSU >
Set_input_delay –min   < tH >
 
(3) input
Set_input_delay –max  < +skew >
Set_input_delay –min   < -skew >
 
(1) output
Set_output_delay -max < tSU + max data delay – min clk delay >
Set_output_delay –min < - tH + min data delay  – max clk delay >
 
(2) output (possibly missing from TimeQuest doc)
 
(3) output
Set_output_delay -max < latch -launch – skew >
Set_output_delay –min  < latch –launch + skew >