Clock Skew doubt

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always @(posedge clock_a) begin

reg_a <= temp;

end

always @(posedge clock_b) begin

reg_b <= reg_a;

end

What happens when I synthesize this? [say clock_a = 22.4Mhz and clock_b = 45.4Mh, assume these frequencies are available]. Will I always get wrong data from reg b?

c. I want to clarify, what should come to my mind when I hear the term "unrelated clock" and "related clock" ?. My understand was, "if two clocks are have different frequencies and if rising_edge_clock_a = n * [rising_edge_clock_b] for n= 1,2,3.. then clocks are related.

d. Does the term "related" and "unrelated" has to do something with the clocks derived from the pll. Eg. all the clocks derived from pll are related [irrespective of the fact that their rising edge may not coincide] with each other.

Thanks,

AA

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knowing just the frequency value is not enough. You need to know phase relationship otherwise I will treat the two clock domains as asynchronous.

by related clocks I mean there is a predefined phase relationship. In other words, the setup or hold relationship is predictable though may change from edge to edge but there will be worst case to be evaluated.

for example if 20MHz clock is to generate two clocks; 25MHz and 50MHz in phase then we know the edges will coincide every other clock of 50MHz. if it has to generate 25MHz and 30 MHz in phase(at the start) then you can draw the two clocks and find out worst case.

In all cases if in doubt you better assume they are asynchronous at some cost.

Moreover, the tool will tell you if it passes or not. If it doesn't then go for clock domain transfer as asynchronous.