Clock Skew doubt

always @(posedge clock_a) begin

reg_a <= temp;

end

always @(posedge clock_b) begin

reg_b <= reg_a;

end

What happens when I synthesize this? [say clock_a = 22.4Mhz and clock_b = 45.4Mh, assume these frequencies are available]. Will I always get wrong data from reg b?

c. I want to clarify, what should come to my mind when I hear the term "unrelated clock" and "related clock" ?. My understand was, "if two clocks are have different frequencies and if rising_edge_clock_a = n * [rising_edge_clock_b] for n= 1,2,3.. then clocks are related.

d. Does the term "related" and "unrelated" has to do something with the clocks derived from the pll. Eg. all the clocks derived from pll are related [irrespective of the fact that their rising edge may not coincide] with each other.

Thanks,

AA