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CFDia's avatar
CFDia
Icon for New Contributor rankNew Contributor
6 years ago

Clock constraint and Dual Data Rate

Hello Dear Friend, I have a design that is now working, but I would like to have some help to improve it. Before asking anything, I would like to make a context like the following description. I am...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

You have mentioned that the direct clock source connected to the ALTDDIO and FIFO just fails. May I know whether it is a compilation error or timing violation?

Thanks.