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Altera_Forum
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17 years ago

Clock characteristics for MAX II devices

Hi Folks, In my board, I want to give 66MHz clock to MAXII CPLD (EPM1270). While referring CPLD datasheet, I can't able to found any recommended clock characteristics (frequency tolerance in pp...
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Altera_Forum
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17 years ago

Jitter is a relevant parameter for FPGA that are driving a PLL from the clock. MAX II has no PLL, so maximum frequency, minimum pulsewidth and rise/fall times are the only parameters of interest.