Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Clock characteristics for MAX II devices

Hi Folks, In my board, I want to give 66MHz clock to MAXII CPLD (EPM1270). While referring CPLD datasheet, I can't able to found any recommended clock characteristics (frequency tolerance in pp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I guess it primarily depends on what the requirements are on the stability of your outputs.

So longs as the jitter is not utterly terrible and your device meets your 66MHz timing requirements then you shouldn't have any internal timings problems