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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock Assignment problem

Hi,

I got a problem with my clock pin assignment. I build up a Nios II core with the following components: clk, on-chip mem, PIOs,SPI,LCD-Character, JTAG UART,SYS ID, Time Intervall. I testet my design with a frequency of 50MHz and it worked. But I want now test it with 125MHz for that reason I assigned the osc_clk from my "Cyclone III 3C120 Development Board" to the Pin A14 but I always get the following message:

Warning: Node: osc_clk was determined to be a clock but was found without an associated clock assignment.

And I don't understand it, because in the manual it says that the PLL for the 125MHz is the Pin A14.

Can somebody help me out of this problem,pleas.

Thanks in advance for the help!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I am not sure...but have you used the sdc constraint file for your osc clock...generally if you define osc_clock in your sdc file...the tool knows your clock or clocks and will automatically route it through global networks..If you stiil have used the sdc file for your osc_clock generation then i am not sure what the problem is...

    good luck
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi siedler

    My guess is that you changed the input clock but the create_clock in the sdc file is still referring to the previous 50MHz signal