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Honored Contributor
Honored ContributorCLK Pins Positive or Negative Edge
Hello People, I have 3 questions about CLK input pins. 1- I see that there are 16 CLK pins on the EP3C25E144 fpga. On the Pin Planner, i see that some of them are positive edge, some ...
Altera_ForumHonored Contributor
Honored Contributor1 - IIRC you should only care if you are using a differential I/O standard for the clock input, and then one pin is the positive input and the other one is negative. If you use a single ended signal you can use any clock input as you wish.
2 - no idea 3 - they should be tied to a stable voltage, either VCCIO or GND. If you leave them floating they could oscillate and cause excessive power drain on the I/O bank.
