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Hi Jan:
The DMA core basically just allows you to initiate a transaction of a specific size to a specific location with minimal CPU overhead. The latency required for the transaction is dependent upon many factors, include arbitration cycles, ram paging etc. A 2 to 1 ratio sounds very reasonable.
This is much faster than A CPU would be able to copy the bytes to the memory via instructions. If you truly need a 1 to 1 for a limited number of cycles, put it into a fifo or TCM (Tightly Coupled Memory).
Pete
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Thanks for the answer... When I was studying about TCM I have read that it is possibile to use only with the internal onchip slave... so I think that my external SDRAM is not capable of TCM.. Am I right?
So only what I can do is to increase the Fclk to the top of the SDRAM possibilities to drag even more speed from DMA?
Thanks for advice