Forum Discussion
Altera_Forum
Honored Contributor
13 years agoIf you want to see a simple buffering sample, head over to the alterawiki and look for the "Modular SGDMA". In the dispatcher block I have a custom FIFO which by definition is a type of circular buffer. If it was me I would implement a controller with Avalon-MM masters on it, one to point at the head and the other points to the tail of the buffer. Then you can hook those masters up to your SRAM slave and not worry about all the interfacing stuff in between. Then your controller just has to ensure the head and tail locations never cross (might be easier with a single master interface).
In case you are wondering why I bothered to write my own FIFO..... I needed shadow registering capabilities to write portions of the FIFO word at a time.