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Altera_Forum's avatar
Altera_Forum
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18 years ago

Check my layout

Hi: This is my first design using CPLD. Can someone comment on my layout before I tell the board house to run it? I'm using an EPM7064STC44-10 Specifically, is my ISP connector correct, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

displaying the flooded bottom layer, the ground connetion looks much better now. Regarding the pullups, the devicé would usually programm without them. Altera USB Blaster has e. g. 100k TCK pulldown, 100k TMS pullup and no TDI pullup. Possible issue is succeptibility to coupled switching noise, that may cause erroneous JTAG circuit behaviour. Thus the suitable resistance value depends on strength of interfering signals. If there isn't plenty of room for additional parts, I would provide a TCK pulldown as minimal means. Pullups at the other pins could possibly slightly reduce supply current.

Regards,

Frank