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Altera_Forum's avatar
Altera_Forum
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18 years ago

Check my layout

Hi: This is my first design using CPLD. Can someone comment on my layout before I tell the board house to run it? I'm using an EPM7064STC44-10 Specifically, is my ISP connector correct, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

I understand, that you have a two layer PCB with GND flooded top layer. Cause GND display is disabled, I can't see how this net is actual connected. Obviously GND connection can't be optimal, the same with supply bypass, but I wouldn't expect particular problems for the CPLD in this design. There may be a danger of double counts and timing violations with a ringing clock, but the said capacitor could help in this case.

TCK should have a pulldown (e. g. 10K), TDI and TMS may have pullups.

Regards,

Frank