Check my layout

Hello,

I understand, that you have a two layer PCB with GND flooded top layer. Cause GND display is disabled, I can't see how this net is actual connected. Obviously GND connection can't be optimal, the same with supply bypass, but I wouldn't expect particular problems for the CPLD in this design. There may be a danger of double counts and timing violations with a ringing clock, but the said capacitor could help in this case.

TCK should have a pulldown (e. g. 10K), TDI and TMS may have pullups.

Regards,

Frank