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I'M now thinking of the format of an entire frame. Each module will have 74 test points. Let's assume it's just 72 bits and we get a nice round figure of 9 bytes.
So, we first send 2-bytes containing the address and then we send 9 bytes of data - obviously if the address doesn't match, the CPLD ignores anything sent afterwards. So essentially we have a 11 byte shift register.
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Yes. Look at the AD9956 document I gave you a link to. It can be similar to that.
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However, how would the uC receive back the data from the CPLDs that specifically are meant for receiving the test-vectors? How about if I make the address 15-bit and make the LSB a Read/Write indicator? If this is 0, the CPLD will send the 9 bytes of data in its shift register. If it's 1, it will shift in new data that it receives just after this Read/Write bit.
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Now go and read the byteblaster interface ... it does something like this.
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I know this is probably inefficient but I'm trying to start out small. As the devices will have a full SPI interface, I can easily upgrade the firmware as I get more experience with VHDL. I've been a C programmer for the past 10 years so VHDL still runs circles around my head.
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"Inefficient" is in the eye of the beholder.
My philosophy is "Get it working first, then get it 'right'". Sometimes 'right' is skipped, since 'working' is often good enough :)
Cheers,
Dave
Honored Contributor
