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I really like the Dip Switch + Internal Address idea. Just so I understand, I'm gonna re-iterate a few things:
1) Each board will have a 4-bit DIP Switch. The first 3-bits identify the board and the LSB identifies weather the CPLD is meant for driving the test vector or receiving it.
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In the case of the two CPLDs, there would only be a 3-bit DIP switch (which both CPLDs see), and the LSB of the address is determined by a CPLD-specific pin - 0 on the first device, 1 on the second.
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2) These 4 bits combined with an 12-bit internal address form a 16-bit address for a CPLD in the system. Just one thing that I still am confused about:
is this 12-bit internal address the same for every cpld?
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The 4-MSBs of the address are determined by the DIP and hard-wired pin (0 or 1), and then remaining address bits are used to access the internals of the CPLD. If all the CPLDs contain the same design, then the 12-bits of address (or 20-bits, or whatever) would access the same design. Alternatively, your driver and receiver CPLDs could have different designs, but that same 12-bits would be accessing their internal memory maps.
Personally I would just create an SPI-to-Avalon-MM master. The 4-bits would be decoded by the master to determine if it was the target, and then the remaining address and data bits would be determined by the rest of the SPI transaction.
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I have a I2C temperature sensor and it has an address of 16-bits. However, the LSB of that address we can clear or set by tying a pin to GND or Vcc. This would sorta be the same, wouldn't it?
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Right, the DIP switch and hard-wired pin (0 or 1) perform this same task; they allow you to take the same 'component' but uniquely identify it.
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I'm asking because I would prefer not to have to tweak a CPLD's 12-bit ID in the VHDL code every time I program a new one. I'd prefer if its a constant and the same for every CPLD.
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You would either use identical designs in all CPLDs, or two unique designs for the two CPLDs on a board. The DIP switch would then define the boards uniquely (3-bit DIP allows 8 unique boards, 4-bit DIP allows 16 unique boards, etc.).
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but as the code may be different for the CPLD that's meant for driving the harness than receiving, I can make the 12-bit address such that the last 4 bit identify weather the CPLD is meant for driving the test vector or receiving it.
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That's the task of the hard-wired pin.
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Essentially, the format is:
BoardID - Internal Address - Driving/Receiving
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Not quite. The CPLD identified is also a high address bit. Lets take your example of a board with ID of 3, a 1-bit CPLD identifier, and a 12-bit internal address. The first CPLD (0) has addresses of the form
011-0-xxxx_xxxx_xxxx
while the second CPLD (1) addresses are
011-1-xxxx_xxxx_xxxx
i.e., the format is BoardID-CPLDID-InternalAddress
The logic inside the CPLD, i.e., on the Avalon-MM bus inside the CPLD, sees the 12-bits of the LSBs, i.e., the xxxx_xxxx_xxxx bits. You can create an SOPC System/Qsys system that is unique to the driver and receiver boards. You would locate board identification registers at address 0 in both designs, and the uC would interrogate them to confirm the CPLDs are loaded correctly.
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We, if we want, can even give the CPLD meant for driving a separate CS line than the ones meant for receiving.
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The two CPLDs are uniquely addressable. What they do it totally up to you.
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3) We can make a simple requirement for the system. All the boards connected to the system must have board IDs in a sequence i.e. if we have 3 boards then the IDs should be 0000b,0001b,0010b. The IDs cannot skip - if they do, we generate an error. We can even put a 3-bit DIP switch on the board with the uC and this switch could set the total number of boards connected to the system. So if this switch reads 4, but there are only three boards connected, it can generate an error. The uC will check this by pinging each board ID from 0000b to 0011b. If 0011b does not respond, we know there is an error.
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Now you're getting the hang of it. You'll end up with a system that abides by rules/conventions, and the micro checks that those rules are followed before allowing testing to progress.
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Regarding the hardware... I'm thinking of going with LVDS Drivers. They look super-easy to implement and the I really like the fact I can run them off 3.3V. If what I've described is good and then I think I will send the following lines to go to the daughterboards:
1) SCK
2) MISO
3) MOSI
4) CS for Driving CPLDs
5) CS for Recieving CPLDs
6) Ground
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You only need one CS. The hard-wired CPLD ID determines which will respond.
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Thank you for the link. I'll study it. I've been studying the ByteBlaster you uploaded for me. Thanks for that, it has been a great help.
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That particular design does not need to decode to multiple boards, but it'll give you a starting point.
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You work in Radio Astronomy! Wow. I'm an amateur astrophotographer myself, in my spare time. :)
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We have some pretty clear skies here. You're welcome to visit!
Cheers,
Dave
Honored Contributor
