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Ah,
of course. So for a 4-bit switch, we'll have 16 board IDs already uniquely defined. 0000b through 1111b. So, suppose, there are 4 boards connected with the addresses: 0000b,0001b,0010b,0011b. As each board has a 74-bit shift register, we know the first board has test-locations 0 through 74, the second has 75 to 149 and on. All of this will be defined in the uC beforehand.
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Right. Depending on how you want your device addressed. The 'local' address map of each CPLD could have fixed length registers, eg. 16-bits wide, so you can have some identification registers at address 0, 1, 2, 3, and then shift registers following that. Or, you can have variable length registers at each address, eg. once you address the shift-register, you need to generate an SPI transaction that fills the whole thing. The AD9956 PLL is an example of a device with variable length shifts to different addresses. Read this doc for an example of the controller design:
http://www.ovro.caltech.edu/~dwh/carma_board/ (
http://www.ovro.caltech.edu/%7edwh/carma_board/)
http://www.ovro.caltech.edu/~dwh/carma_board/ad9956_tests.pdf (
http://www.ovro.caltech.edu/%7edwh/carma_board/ad9956_tests.pdf)
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However, how would know uC know how many boards are connected? Or does it simply not matter? If there is no board with an address of 0100b, the uC receives no response.
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The test program should know how many boards are connected, and it can then go and check they exist. For example, the micro can go and read the CPLD image identification registers at address 0, 1, 2, 3, and make sure each responds with the correct info, eg., a version number, build timestamp, etc.
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At startup, the uC can send a ping to all 16 addresses. So suppose it pings 0000b. If it receives no response, it knows there is no board connected there. It then pings 0001b, it the board pings back then the uC knows there is a board connected there.
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Right. It can do that and if it is expecting a board at address 0000b and does not find one, then it can report an error.
At some point in the system design, you have to tell the software what to expect to find, and then generate a warning when there is an inconsistency with what it finds.
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Yes, as I was reading this thread I felt I2C might work better as it already has addresses in the protocol.
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The key is to realize that you can define a protocol. It really just comes down to whether your uC's I2C controller can do what you want, or the SPI controller, or GPIO pins.
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What I meant was, if each board will really ever contain 2 CPLDs (one for output and another for input)
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Why would you need one for output and one for input? The pins are bidirectional, so both should have the outputs read-back. I guess you are referring to one as your driver into the harness (with read-back), and one at the end of the harness for read-back.
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can the board ID not be used as the CPLD ID? We really don't have any plans for cascading more than 6 boards - each board having two CPLDs (o/p and i/p each).
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Sure, but in this case, you could have a 4-bit board ID, with 3-bits set by the DIP, and the LSB set by a pin on the CPLD, i.e., the first CPLD on the board has an LSB of 0 and the other 1.
Cheers,
Dave
Honored Contributor
