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Do you mean like this, except that CS would also be common for all CPLDs?
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Right - just like if you had the components all on the same board.
As you see from your diagram, the difficulty is that you have to have a CS per device.
JTAG gets around this by cascading all the devices in a daisy chain - so you can do the same thing if you like.
I2C gets around this by having each device uniquely identified.
Dallas 1-Wire devices get around this by having a 64-bit unique ID.
So, you can leverage any of these methods - whichever happens to work for you.
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If this is the case, then basically the uC will treat the CPLDs not as a giant shift register but really as multiple small ones. Let's assume I have 8 bit input vector 00001000. Let's further assume that my CPLDs can only implement 2 bit shift registers, so I need four of them.
The output of the above test-vector is 10110001. The first CPLD is 10, second 11, third 00 and fourth 01. The uC will first address the 1st CPLD and read back it's contents. Then it will send the same instruction but instead of addressing the first one, it will address the 2nd one and so on.
Is my understanding of this, at a high level, correct? If so, I quite like this. It's elegant, simple and robust.
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Yes, that is correct. Your test system is composed of uniquely addressable devices.
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My only confusion now is regarding addresses of the CPLDs. You mention having a 4-bit DIP Switch that could be used as a board ID. How would know the uC know the value of each DIP Switch?
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You have to know what you are physically connecting to, i.e., the wires in the test harness, so you have to define what the board IDs connected to what are. You could define the DIP switch setting of 0000b as the first board, 0001b as the second board etc.
In our systems, we have Dallas 1-Wire ID EEPROMs at physical locations. When you plug a generic module (FPGA+microcontroller) in, the location EEPROM contents are read, and that defines the module location address.
In your case, when you plug the board in, you flip the DIP switches.
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I could see it working if its located on the main board. If the switch reads 12, the uC knows the total number of boards is 12 and their addresses start from 1 to 12. Is this what you meant?
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No. Its an address for decoding. If there is no board with the DIP switch set to 0000b, then there will be no response to an SPI transaction with the device ID bits set to 0000b, i.e., all the CPLDs decode the ID and find that its not them.
Go and read about how I2C devices work. This is sort of the same scheme, except that there is a unique line for output versus input data. The separate lines allow for differential drivers, rather than a common driver. You could in fact use I2C to implement your system too (isolators exist, and I2C is deploying in buildings single-ended, so its fairly robust).
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Also, why the need for 12-bit internal address for each CPLD? Will this be hard-coded in?
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You'd need to define the SPI protocol so that your micro can address devices. You can define an address of 32-bits, but then you'd be wasting your time if you're only addressing a few hundred unique locations. So, you write the code with generics, but ultimately you need to synthesize with a fixed value.
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Thank you
very much for all the help you've given me. It would have taken me months to get through any of this stuff. Please know your help is immensely appreciated.
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You are more than welcome. Once you've figured out the approach you'd like to use, I'll review it for you. The nice thing about hardware languages is that it costs you nothing to build a system in simulation.
Cheers,
Dave
Honored Contributor
