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You can treat your SPI bus as a common bus with MOSI going to all the devices in parallel, and MISO coming from all in parallel. This is where the device ID would be useful, as only the selected device would drive the common MISO bus.
Alternatively, you do the JTAG trick where the shift-register passes through all the devices and then loops back to the master. That'll provide the read-back function.
Cheers,
Dave
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Do you mean like this, except that CS would also be common for all CPLDs?
http://i.imgur.com/CaGEt.png If this is the case, then basically the uC will treat the CPLDs not as a giant shift register but really as multiple small ones. Let's assume I have 8 bit input vector 00001000. Let's further assume that my CPLDs can only implement 2 bit shift registers, so I need four of them.
The output of the above test-vector is 10110001. The first CPLD is 10, second 11, third 00 and fourth 01. The uC will first address the 1st CPLD and read back it's contents. Then it will send the same instruction but instead of addressing the first one, it will address the 2nd one and so on.
Is my understanding of this, at a high level, correct? If so, I quite like this. It's elegant, simple and robust. My only confusion now is regarding addresses of the CPLDs. You mention having a 4-bit DIP Switch that could be used as a board ID. How would know the uC know the value of each DIP Switch?
I could see it working if its located on the main board. If the switch reads 12, the uC knows the total number of boards is 12 and their addresses start from 1 to 12. Is this what you meant?
Also, why the need for 12-bit internal address for each CPLD? Will this be hard-coded in?
Thank you
very much for all the help you've given me. It would have taken me months to get through any of this stuff. Please know your help is immensely appreciated.
Honored Contributor
