--- Quote Start ---
I strongly suspect your measurement is wrong.
The main concern in the design of TDC on fpga is that your signal input will be asynchronous and can't be sampled on registers without timing violation. It also can't be synchronised through two stage registers as this will defeat the purpose.
So I don't see how TDC can sort out this issue.
--- Quote End ---
Although talking about TDC implementation in FPGA is not my purpose of this thread, i will input some more words as your concern.
Yeah, as you said, external signal input are totally asynchronous. when a hit signal arrives, a carry signal will be generated and this carry signal will propagate along the tapped delay line which is created with carry chain (cascaded carry LEs in Cyclone-IV). for example, in Cyclone-IV, average carry delay is 45ps at room temperature. so in worst case, only the most front register where carry signal reaches may run into metastability(this may need some more thinking). since TDC implemented in FPGA is somewhat of statistical meaning, and on-line calibration is also employed to revise result, so it is ok for last bit instability.
As to my test result, the same method is also used to measure carry delay in Cyclone-IV and the test result is 45ps under room temperature which is well fiitted into timequest result. I rechecked my method in Cyclone-V, and i did not find any problem with my method.
i think i need a definitive answer, or maybe i need send a service request to Altera?
Best Regards,
ingdxdy
Honored Contributor
