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Altera_Forum's avatar
Altera_Forum
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13 years ago

Can't generate netlist output files

hi, am using TSE mac ip for my project, while compiling upto timequest timing analysis it was succesfull, SOF file is also created, but in EDA netlist writer am getting this below error. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No it's not possible. You can simulate the individual components, but if you really want to simulate the full compiled design, you will need the licenses. You could ask your university if they have them.