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Rmc_Arira's avatar
Rmc_Arira
Icon for New Contributor rankNew Contributor
6 years ago

Can't access Jtag error

I am using a MAX 10 device: 10M04SCU169C8G I used Quartus 17.0 to synthesize and build the FPGA I have tried using the stand alone programmer versions 17 and 18. I have tried two different byt...
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
6 years ago

Hi,


CRC-Error open drain has dual purpose pin which are pull up(enable) and pull down(disable). Intel recommends you to tie the CRC_ERROR pin to VCCIO, GND, or leave the pin unconnected when the CRC error detection circuitry is disabled or when you are not using the CRC_ERROR pin.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/PCG-01018.pdf


You can try to go to Quartus -> Convert programming file -> Advance -> Tick both boxes ( Disable EPCS and disable AS mode).


Regards,

Aiman