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Altera_Forum's avatar
Altera_Forum
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14 years ago

Can't access JTAG chain: Stratix III dev board

Hi, I am using a StratixIII development board EP3SL150F1152 with QuartusII 9.1 on Windows 7 and was trying to download the ".sof" example that comes with the development kit to do a prelimina...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I'm not sure of the switches orientations and I don't have a kit here to check it, but the first signal I would check is the MAX_ENABLE (4th contact on SW1). It controls the MAX_OE signal, and must be at a high level to enable the MAX II. This means that the contact must be open. If necessary check with a voltmeter that the signal is indede high.

The .sof file that you uploaded was just put into the FPGA's RAM and probably hasn't changed the flash memory. Turning the power off and on again should have reloaded the default setting from the flash. If it doesn't do so it is either because of a hardware failure, or a switch configuration that prevents the MAX II from loading the correct configuration into the FPGA.

If you are still stuck you should contact a local Altera representative to see if they can help you figure out what's wrong with the board.