Forum Discussion
mbran15
New Contributor
New Contributorcan i use quick sorting in HDL(Verilog or VHDL)?
module sort_ex ( clk, rst, out);
parameter SIZE = 10;
input clk, rst;
output reg [6:0]out;
reg set_end, loop_check, loop_on1, loop_on2, loop_on3;
reg [8:0] arr [SIZE-1:0];
reg [8:0] temp;
reg ...
GuaBin_N_Intel
Contributor
ContributorSome of C/C++ coding may not be synthesized correctly even though sometime it can compile successfully. Advice you can copy out what error you had in here or search any solution/hint to that error in quartus help https://www.intel.com/content/www/us/en/programmable/quartushelp/18.0/index.htm#msgs/msgs/wsta_launch_latch_overflow.htm
