Can cyclone III comes into the user mode if AP config failed?

Thank you everyone, I have resolved the problem, that's really cause by the POR error, the solder is really ok!

I find that the wire of the VCCA and VCCD_PLL must >20mil emphasized on the datasheet, but the inductor connect the VCC_1V2 and VCC_2V5 to these power pins may

a bit thin, I replace it with a thick BEAD or large 0 Ohm resister, then I can find the device EP3C120F780I7 through JTAG, yes this.

The nSTATUS signal, by the way, is a periodic pulse from the scope, I think it is excuting the reconfiguration repeatedly, why? I analyzed the reason, and explain it that the package of the intel P30 flash which I used on this board is a TSOP type, the FPGA can shake hands with it in asynchonize mode, but can't implement the AP config loading, for this TSOP package isdosen't support the synchonize burst read, data loding failure, then it repeat..., but this dosen't prevent the JTAG debug, the JTAG has a higher priority, I think so.

Then, I try to pull-down the ADV signal of the P30 flash to forbid the synchronize mode, I find that the periodic pulse of the nSTATUS disappeared, it keep the high level, the JTAG debug also to use ok.

Next step, I must replace this TSOP package to the new Micron 65nm SBC version, I find it really supports the sync burst read from the new distributed datasheets.

Who known the new Micron 65nm SBC version P33 flash (TSOP package)?

I will share the debug info on this issue, please stay tuned.