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Altera_Forum
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18 years ago

Can conditional builds be performed in VHDL?

I'm relatively new to VHDL and am looking for a way to perform conditional builds. I'm aware of the `ifdef that is available in Verilog, but am trying to find a comperable method in VHDL.
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi wolson,

As I am a quite lazy, each time I have a repetitive structure to implement, I use the FOR-GENERATE statement (I am rather keen on coding with AHDL instead of VHDL but it's very similar).

That works well nevertheless when it comes to use the PARAMETER statement (to parameterize a port size for instance), I do have some trouble to pass the parameters down along the project hierarchy (from the top-level entity to lower level entities).

The "parameter value search order " section given in the Qts II help is a bit confusing so I was wondering whether you experienced a similar problem (I'm often use the PARAMETER statement in BDFs) ? ...

Thanks.

Oliver